The complexities and uncertainties associated with the manufacturing of semiconductor products (“chips”) requires that some level of testing be performed on each chip before being shipped to customers. The extent of testing can range from sample testing for chips deploying straightforward designs and mature manufacturing processes, to several stages of lengthy, fully-functional, multi-temperature testing for chips using the latest technologies.
The automatic test equipment (ATE) used to perform the tests on semiconductor chips provide the stimulus to the chip, as well as capture and process the response from the chip, all under computer control. Since ATE must be able to source and capture many channels of the latest high-speed, smart-power, and high-precision signals, the ATE business model requires significant investments in research and development, applications engineering, and other support functions. The current industry average selling price for ATE is therefore in the range of $US0.5 million to $US1.5 million.
In order to manage the overall cost of test, ATE will typically be configured to have only the channels and capability needed to test a particular chip, making the manufacturing capacity provided by the ATE dedicated to a given chip, or at best, a chip family. Each ATE supplier, too, has a different architecture and set of channel attributes, adding another dimension of complexity and incompatibility to the test capacity. In addition, each chip has a unique list of required tests, making the cycle time through the test process chip-dependent. Furthermore, each chip requires a specific combination of peripheral components and equipment (e.g. interface fixtures and sockets, handling equipment and kits, etc.) that together with the ATE complete a full “test cell” of capacity. The many cells of semiconductor test capacity required today are therefore very diverse and non-uniform.
This variability makes it difficult for test providers to optimize the utilization of costly test assets and thus maximize their return on investment (ROI)—reducing the economic profits of not only the test provider, but also that of the test specifier and test equipment supplier. This issue is even more of a problem for the test subcontractor, whose founding business model relies on the efficient aggregation of test demand across a diverse set of test specifiers and their chips. The typically-cited one-third of test capacity that is unutilized accounts for an estimated US$1.8 billion of annual depreciation costs, a significant economic burden on the entire semiconductor test value chain.
The landscape of solutions related to semiconductor test generally addresses both low and high levels of operations abstraction, but leaves a conspicuous gap at the test capacity planning level. At the low level, the solutions ignore the chip's test capacity requirements and therefore cannot perform any of the test capacity planning functions needed to significantly improve ROI. Just above the low end are tools focused on overall equipment efficiency (OEE) which lack the demand aggregation and configuration management capabilities required of a value-adding test capacity planning solution. At the high level, well-known supply chain management, demand management, and business intelligence offerings treat test capacity simply as a “black box,” precluding any useful planning functionality that accounts for the non-uniformity of test capacity. At the test capacity management level are numerous, incompatible, obvious and rudimentary spreadsheet solutions that severely lack the detailed modeling sophistication and resulting precision and accuracy that are needed today.
Thus, a solution is needed that enables sophisticated planning of configurable manufacturing capacity, like that which is used for testing of semiconductor chips.